Conference Program is now available!

Best Paper Nominees & Best Paper Awards

ISVLSI 2025

Contributions are sought in the following tracks:

• Circuits, Reliability, and Fault-Tolerance (CRT):
  Analog/mixed-signal circuits design and testing, RF and communication circuits, adaptive circuits and interconnects, design for testability, online testing techniques, static and dynamic defect- and fault- recoverability, variation aware design, VLSI aspects of sensor and sensor network.
• Computer-Aided Design and Verification (CAD):
  Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.
• Digital Circuits and FPGA based Designs (DCF):
  Digital circuits, chaos/neural/fuzzy-logic circuits, high speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
• Emerging and Post-CMOS Technologies (EPT):
  Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
• System Design and Security (SDS):
  Structured and custom design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, hardware security, cryptography, watermarking, and IP protection, TRNG and security-oriented circuits, PUF circuits.
• VLSI for Applied and Future Computing (AFC):
  Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.

Selected papers from ISVLSI 2025 (main tracks & special sessions) will be invited for submission to special issue on IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Journal on Emerging Technologies in Computing Systems. The selection process is based on reviewers' feedback and quality of conference presentation.

Extended versions of papers accepted  in Quantum Computing Workshop will be invited to peer-reviewed journals such as ACM Transactions on Quantum Computing and Springer Nature Computer Science.

Important Dates

Author Guidelines

Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. Previously published papers or papers currently under review for other conferences/journals should NOT be submitted and will not be considered. To enable blind review, the author list should be omitted from the main document. The manuscript as a single PDF is to be submitted online through Easychair. The manuscript as a single PDF is to be submitted online through Easychair. The IEEE Manuscript Template for Conference Proceedings should be used, which can be found here.

More information can be found on the Paper Submission page.

For information regarding visa requirements for travel to Greece, we recommend referring to the conference venue section, where you will find the most up-to-date and relevant details to assist with your travel preparations.

Conference Program

All times listed below are in GMT+3 Time Zone (Athens, Greece)

*On-site registration and conference materials collection will also be available at the registration desk throughout the entire duration of the conference

The official ISVLSI 2025 conference booklet is available for download

🎓Best Paper Nominees – ISVLSI 2025 🏆

We are pleased to announce the Best Paper Nominees for IEEE ISVLSI 2025. These papers have been selected by the Technical Program Committee based on their originality, technical depth and potential impact on the field.

Best Paper Nominees:

• 📄  HEDGY: Heterogeneous Design Management for Multi-Tenant Multi-FPGA Edge Systems - Ian Kersz, Arthur Ely, Pedro Alles, Michael Jordan, José Rodrigo Azambuja, Fernanda Kastensmidt and Antonio Carlos Schneider Beck. Universidade Federal do Rio Grande do Sul, Brazil
• 📄 Towards Improving Performance Metrics of Minority Majority Inverter Graph (mMIG) Circuits - Mrunal Shende and Bodhisatwa Mazumdar. 
• IIT Indore, India
• 📄 EXAMINER: IP Extraction Algorithm for MAGIC Logic-in-Memory -  Lorenzo Pfeifer, Rainer Leupers and Jan Moritz Joseph. RWTH Aachen University, Germany
• 📄 Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware Accelerators, Pruthvi Parate, Daksh Sharma, Alwin Shaju and Madhav Rao. IIIT Bangalore, India
• 📄 Sparse-Aware NTT: Accelerating Lattice-Based Cryptography on FPGAs - Dixit Dutt Bohra, Dip Sankar Banerjee and Somitra Sanadhya. Indian Institute of Technology Jodhpur, India
• 📄 Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks - Devon Lister, Prabhu Vellaisamy, John Shen and Di Wu. University of Central Florida, USA; Carnegie Mellon University, USA
• 📄 Flip-UnLock: An Anomaly Detection Attack on Flip-Flop-Based Logic Locking - Armin Darjani, Nima Kavand and Akash Kumar. Ruhr University Bochum, Germany; Technical University of Dresden, Germany
• 📄 RAT: RFET-based Analog Hardware Trojan - Nima Kavand, Armin Darjani, Tushar Niranjan and Akash Kumar. Technical University of Dresden, Germany; Birla Institute of Technology & Science Pilani, India; Ruhr University Bochum, Germany
• 📄 A Low-Complexity XOR-Based BCH Decoder for PAM4 Modulation Systems - Changfu He, Xinle Jia, Yuxing Chen, Wenli Xu, Suwen Song and Zhongfeng Wang. Nanjing University, China; Sun Yat-sen University, China
•  📄 A 6T SRAM based reconfigurable in-memory  XOR/XNOR and accumulation architecture - Cheena Singhal and Sparsh Mittal. IIT Roorkee, India
•  📄 Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering - Leon Li and Alex Orailoglu .University of California, San Diego, USA
•  📄 A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning Applications - Sepideh Kheirollahi, Sinatra Babele Khanshan and Zainalabedin Navabi. University of Tehran, Iran
•  📄 Real-time Padel Strokes Classification. Georgios Papaspyropoulos, Evanthia Faliagka, Theodoros Skandamis - Christos Antonopoulos and Nikolaos Voros. University of the Peloponnese, Greece
•  📄 SIC Design Flow Using Simulink and Cadence Digital IC Design Tools - Ava Hedayatipour, Charanya K Rao and Ashmitha Talluri. California State University, Long Beach, USA
•  📄 Α Νοvel Firmware Architecture leveraging Race to Sleep paradigm for Ultra-Low-Power CPS - Angelos Smyrilios, Evanthia Faliagka, Alexandros Spournias, Christos P. Antonopoulos and Nikolaos Voros. University of the Peloponnese, Greece
• 📄 MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications - Sahar Moradi Cherati and Leonel Sousa. University of Lisbon, Portugal
• 📄 Accelerating Equation Solvers using Gauss-Jacobi on Multi-FPGA Systems with Ring NoC - Shruti Patkar, Harsh, Souraja Kundu and Gaurav Trivedi. Indian Institute of Technology, India
• 📄 Aging Model Development for ASAP 7 nm PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition System - Neha Gupta, Lomash Chandra Acharya, Mahipal Dargupally, Khoirom Johnson Singh, Amit Kumar Behera, Johan Euphrosine, Sudeb Dasgupta and Anand Bulusu. Indian Institute of Technology, India; Google Inc., USA
• 📄 Real-Time Person Recognition Using MoveNet for Pose-Based Identification. Evanthia Faliagka, George Tefas, Christos P. Antonopoulos and Nikolaos Voros. University of the Peloponnese, Greece

🏆 IEEE ISVLSI 2025 – Best Paper Awards 🏆

The IEEE ISVLSI 2025 Organizing Committee is delighted to announce the recipients of the Best Paper Awards, recognizing outstanding contributions to the field of Very Large Scale Integration.

🥇 Amar Mukherjee Best Paper Award of ISVLSI 2025

Paper Title: Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural Networks
Authors: Devon Lister, Prabhu Vellaisamy, John Shen and Di Wu
Affiliations: University of Central Florida, USA; Carnegie Mellon University, USA

🥇 Nagarajan Ranganathan Best Paper Award of ISVLSI 2025

Paper Title: EXAMINER: IP Extraction Algorithm for MAGIC Logic-in-Memory
Authors: Lorenzo Pfeifer, Rainer Leupers and Jan Moritz Joseph
Affiliation: RWTH Aachen University, Germany

🥇 Best Poster Award of ISVLSI 2025

Paper Title: RAT: RFET-based Analog Hardware Trojan
Authors: Nima Kavand, Armin Darjani, Tushar Niranjan and Akash Kumar
Affiliations: Technical University of Dresden, Germany; Birla Institute of Technology & Science Pilani, India; Ruhr University Bochum, Germany

🥇 Best Student Paper Award of ISVLSI 2025

Paper Title: MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing Applications
Authors: Sahar Moradi Cherati and Leonel Sousa
Affiliation: University of Lisbon, Portugal

🥇Best Paper Awards of the ISVLSI 2025 Workshop on Quantum Computing

Paper Title: RaptorQu: Electromagnetic Modeling of Superconductors
Authors: Konstantinos Nikellis, Garth Sundberg, Yiannis Moisiadis and Stefanos Stefanou
Affiliation: Ansys, Inc.

Paper Title: Q-Fusion: Diffusing Quantum Circuits
Authors: Collin Beaudoin and Swaroop Ghosh
Affiliation: The Pennsylvania State University

Paper Title: Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural Networks
Authors: Sounak Bhowmik, Travis Humble and Himanshu Thapliyal
Affiliations: Oak Ridge National Laboratory, University of Tennessee - Knoxville

Paper Title: Breaking Down Quantum Compilation: Profiling and Identifying Costly Passes
Authors: Felix Zilk, Alessandro Tundo, Vincenzo De Maio and Ivona Brandic
Affiliation: Technical University of Vienna

These papers were selected based on technical quality, originality, clarity, and relevance by the Technical Program Committee.

We congratulate the winners and thank all authors for their valuable contributions to ISVLSI 2025!

Organizers

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